WatchReal vs Hype18 Jul 20262:54 watch2 min readSemiconductors: chips, fabs & yield

Chips Just Got Flipped Over — Why Your Next AI Chip Gets Power From the Back

The Great Flip: How Backside Power Put Intel Back Ahead of TSMC

A wafer held vertically on edge on a bench, its underside catching warm gold light
The picture for this piece. Made for it: no people, no brands.

In plain words

For sixty years a chip carried power and data on the same side. Intel just flipped it over.

As transistors shrank to 2 nanometres, the front of the chip ran out of room. Fat power wires choked the thin signal wires.

The fix is not a smaller transistor. It is turning the finished wafer upside down and moving all the power wiring to the back.

Signal on the front, tuned for speed. Power on the back, clean and uncrowded.

Intel shipped it first, and it put them back ahead of TSMC on this one feature.

Why is it hard? The wafer has to be thinned from about 700 microns to about 1 micron, and that is manufacturing, not design.

Picture it. A house where the plumbing and the wiring shared one wall until the wall ran out of room, so the plumbing moved to the basement.

Why it matters to you. Give your AI the recipe, not the mystery. Ask it to apply control limits to your data and flag what drifts, the way a process engineer would.

Terms in this piece

TSMC Taiwan Semiconductor Manufacturing Company
The world's largest contract chip maker; it makes most advanced AI chips.
SPC Statistical Process Control
Watching a process with control charts so a drift is caught before it becomes a bad part.
Watch on the channelOpen on YouTube

The number

700µm → 1µm

WAFER THINNED FOR BACKSIDE POWER · INTEL POWERVIA · 2026

What to do Monday

Stop asking AI to "find the problem" in your process data — give it the recipe. In ChatGPT/Copilot data analysis: "treat this as SPC — control limits from the baseline, flag any point past 3σ AND any run of 7 on one side, ranked by severity." Tested on a thinning-step log: it caught a slow drift 7 readings before the hard excursion.

In the video

  1. 0:0060 years on the same side

The honest caveat

Intel shipped first, but TSMC has announced its own version and has ramped hard nodes before. Thinning a wafer to about one micron is hard, and yield numbers for it are not public. Ahead on one feature is not ahead on the node.

Your turn

Pure manufacturing race now — who holds the backside-power yield lead in 18 months: Intel (first to ship) or TSMC (deepest process muscle)?

Argue with me on LinkedIn

Sources

The run's own source list was not recorded. These are the sources the piece names in its own words, listed here so every claim has an owner.

  1. PrimaryIntel — PowerVia, the first backside power delivery to ship, on the 18A process (Intel, 2026)
  2. As citedWafer thinning from about 700 microns to about 1 micron for backside power, an industry figure as stated in the piece